View ENA1787A_5965311.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

specifications of any and all sanyo semiconductor co.,l td. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' sproductsor equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general el ectronics equipment (home appliances, av equipment, communication device, office equipment, industrial equ ipment etc.). the products mentioned herein shall not be intended for use for any "special application" (medica l equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, t ransportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of re liability and can directly threaten human lives in case of failure or malfunction of the product or may cause har m to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for app lications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. if there is n o consultation or inquiry before the intended use, our customer shall be solely responsible for the use. d2210 sy/82510 sy 20100818-s00003 no.a1787-1/12 lv8415cb overview lv8415cb is blurring correction driver ic for dsc. functions ? actuator driver (saturation drive h bridge) 2ch ? hall amplifier 2ch ? constant current hall bias circuit 2ch ? general-purpose amplifier 2ch ? with built-in for pwm signal generation logic circuit 2ch ? 8bitdac for hall bias 2ch ? 8bitdac for hall amplifier offset adjustment 2ch ? three line serial input ? two systems in power supply (v m : for actuator, v cc ) ? with built-in thermal protection circuit ? with built-in low voltage malfunction prevention circuit specifications maximum ratings at ta = 25 c parameter symbol conditions ratings unit supply voltage 1 v m max 6v supply voltage 2 v cc max 6v output peak current i o peak out1 to 2 (t 10msec, duty 20%) 600 ma output current i o max out1 to 2 350 ma hall bias current i hb max 5ma allowable power dissipation pd max on a specified board * 1 w operating temperature topr -20 to +85 c storage temperature tstg -55 to +150 c * specified board: 40.0mm 50.0mm 0.8mm, four layers fiberglass epoxy circuit board. allowable operating ratings at ta = 25 c parameter symbol conditions ratings unit supply voltage range 1 v m 2.7 to 5.5 v supply voltage range 2 v cc 2.7 to 5.5 v logic input voltage v in 0 to v cc +0.3 v bi-cmos integrated circuit blurring correction driver ic for dsc h bridge 2ch driver orderin g numbe r : ENA1787A
lv8415cb no.a1787-2/12 electrical characteristics at ta = 25 c, v cc = 3.3v, v m = 5.0v ratings parameter symbol conditions min typ max unit current consumption when standing by i cco st = ?l? 1.0 a vm current consumption i m v m = 5.0v, st = ?h?, no load 10 a v cc current consumption i cc st = ?h?, no load 2 3.2 ma v cc low voltage cutting voltage vthvcc 2.1 2.4 2.6 v low voltage hysteresis voltage vthhys 100 150 200 mv thermal shutdown temperature tsd design guarantee 155 175 195 c thermal hysteresis width tsd design guarantee 15 35 55 c h bridge output (out1-2) ronu i o = 100ma, upper-side on resistance 0.7 0.98 output on resistance rond i o = 100ma, under-side on resistance 0.5 0.7 output leakage current i o leak 1 a diode forward voltage vd id = -100ma 0.7 v operational amplifier (op-amp1-4) input offset voltage op_vio 1 5mv input offset current op_iio 5 50 na input bias current op_ib 30 250 na equal phase input voltage range vicm 0 v cc v equal phase signal removal ratio cmr 60 80 db large amplitude voltage range vg r l = 20k , vin = 1mv(open loop gain) 1 10 v/mv v o h r l = 20k v cc -0.2 v output voltage range v o l r l = 20k 0.2 v power supply change removal ratio svr 65 85 db output current (sink/source) op_io 1 2 ma hall bias (hb1-2) output current ihb rhg = 1k , vhbin = 1.0v 0.95 1.00 1.05 ma output saturation voltage vsathb i hb = 1ma v cc -0.2 v standard voltage standard voltage vref 1.60 1.65 1.70 v standard voltage load characteristic vrref i ref = 100 a 1.60 1.65 1.70 v internal clk frequency for pwm drive clk frequency fclk 13.5 15 17.25 mhz control pin (st, sclk, data, stb) built-in pull-down resistance rin 50 100 200 k i in l v in = 0v 1.0 a input current i in h v in = 3.3v 20 33 50 a input ?l? level voltage v in l 1.0 v input ?h? level voltage v in h 2.5 v
lv8415cb no.a1787-3/12 package dimensions unit : mm (typ) 3397 pin assignment sanyo : wlp32(2.47x2.47) side view top view side view bottom view 0.245 fedcba 0.69 max 0.175 2.47 2.47 1 2 3 4 5 6 0.4 0.235 0.235 0.4 out 1a out 1b pgnd out 2a out 2b (nc_ test) vref stb data sclk st vm v cc v in +3 v in -3 hb1 hb2 sgnd v in +4 v in -4 v in +1 v in -1a v in -1b v in -2b v in -2a v in +2 hgnd1 vout 3 vout 1 vout 2 vout 4 hgnd2 f e d c b a 1 2 3 4 5 6 ball side view power supply pin gnd pin output pin logic control pin analog control pin (nc_test) is pin only for the test. please nc_testpin connect gnd line pd max - ta 0 0.2 1.2 -30 90 60 30 0 120 0.8 0.4 0.6 1.0 0.52 ambient temperature, ta -- c allowable power dissipation, pd max -- w specified circuit board: 40.0 50.0 0.8mm 3 four layer glass epoxy board
lv8415cb no.a1787-4/12 pin function pin no. pin name pin function equivalent circuit e2 e3 e4 e5 st sclk data stb input pin. high level 2v to (v cc = 3.3v) low level 0 to 0.5v (v cc = 3.3v) f1 f2 f4 f5 e1 f3 out1a out1b out2a out2b vm pgnd output pin. (pwm output) vm : power ? power supply pin. pgnd : power ? gnd pin. d1 d6 v cc sgnd signal system power supply pin signal system gnd pin c1 b1 c6 b6 hb1 hgnd1 hb2 hgnd2 hb1, 2 pin hall bias source pin hgnd1, 2 pin hall bias current setting pin a1 a2 a3 a6 a5 a4 v in +1 v in -1a v in -1b v in +2 v in -2a v in -2b hall amplifier input pin v in + hall amplifier+ input pin v in -a hall amplifier- input pin v in -b lpf formation pin (the filter is formed for the noise removal.) b3 b4 vout1 vout2 hall amplifier output pin. vout1 : hall amplifier 1ch output pin. vout2 : hall amplifier 2ch output pin. continued on next page. gnd in v cc ot ot pg vm in hb gnd v cc hgnd in+ gnd v cc ina inb ot v cc gnd
lv8415cb no.a1787-5/12 continued from preceding page. pin no. pin name pin function equivalent circuit d2 c2 d5 c5 v in +3 v in -3 v in +4 v in +4 general purpose amplifier input pin. v in +3 : 3ch general purpose amplifier+ input pin v in -3 : 3ch general purpose amplifier- input pin v in +4 : 4ch general purpose amplifier+ input pin v in -4 : 4ch general purpose amplifier- input pin b2 b5 vout3 vout4 general purpose amplifier output pin. vout3 : 3ch general purpose amplifier output pin vout4 : 4ch general purpose amplifier output pin e6 vref internal standard voltage pin v cc /2 output f6 nc-test n.c. pin test pin please nc_testpin connect gnd line in+ gnd v cc in- ot v cc gnd gnd v cc vref gnd v cc nc
lv8415cb no.a1787-6/12 block diagram out1a vm out1b out2a out2b pgnd + - st v in -4 v in +4 vout4 + - v in -3 v in +3 vout3 + - v in -2b v in -2a vout2 + - hgnd2 hb2 + - v in -1b v in -1a vout1 v in +2 8bit dac v in +1 8bit dac 8bit dac h + - hgnd1 hb1 8bit dac h + - vref pgnd v cc sclk data stb hall out (yaw) hall out (pitch) logic-chip h bridge circuit h bridge circuit logic circuit logic circuit 10 bitpwm generation logic 10 to 12bitpwm generation logic overheating protection circuit oscillation circuit v cc low voltage cutting circuit sirial /pararel standard voltage setpoint signal (3 line sirial)
lv8415cb no.a1787-7/12 3 line serial communication electrical characteristics at ta = 25 c, v cc = 3.3v, v m = 5.0v ratings parameter symbol conditions min typ max unit serial data forwarding pin i in l v in =0v(sclk, data, stb) 1.0 a logic pin input current i in h v in =3.3v(sclk, data, stb) 33 50 v input ?h? level voltage v in h sclk, data, stb 2.5 v input ?l? level voltage v in l sclk, data, stb 1.0 s minimum sclk ?h? pulse width t sc h 0.1 s minimum sclk ?l? pulse width t sc l 0.1 s stb regulation time tlat 0.1 s minimum stb pulse width tlatw 0.1 s data set-up time tds 0.1 s data hold time tdh 0.1 s maximum clk frequency fclk 4 mhz serial data timing condition serial data input timing chart it inputs it from a0 in order of d11. the data transfer is d one by the rising edge, and after all data transfers, the latch does all data to sclk by the stb signa l standing up. the stb signal accepts and the internal logic of ic doesn't accept the sclk signal during "h". sclk data stb t sc h t sc l fclk tds tdh a1 a0 a2 tlat tlatw d10 d11 a0 a1 a2 a3 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 st data sclk stb the latch does the state setting data
lv8415cb no.a1787-8/12 serial logic map pwmh - bridge relation serial map input a0 a1 a2 a3 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 setting mode set content remarks * * 0 0 0 0 0 0 0 0 0 0 100% * * 1 0 0 0 0 0 0 0 0 0 511/512 100% * * 0 1 0 0 0 0 0 0 0 0 510/512 100% * * 0 1 1 1 1 1 1 1 1 0 2/512 100% * * 1 1 1 1 1 1 1 1 1 0 1/512 100% reverse * * 0 0 0 0 0 0 0 0 0 1 0% middle point * * 1 0 0 0 0 0 0 0 0 1 1/512 100% * * 0 1 0 0 0 0 0 0 0 1 2/512 100% * * 1 0 1 1 1 1 1 1 1 1 509/512 100% * * 0 1 1 1 1 1 1 1 1 1 510/512 100% 0 0 0 0 * * 1 1 1 1 1 1 1 1 1 1 1ch pwm duty set 511/512 100% normal rotation * * 0 0 0 0 0 0 0 0 0 0 100% * * 1 0 0 0 0 0 0 0 0 0 511/512 100% * * 0 1 0 0 0 0 0 0 0 0 510/512 100% * * 0 1 1 1 1 1 1 1 1 0 2/512 100% * * 1 1 1 1 1 1 1 1 1 0 1/512 100% reverse * * 0 0 0 0 0 0 0 0 0 1 0% middle point * * 1 0 0 0 0 0 0 0 0 1 1/512 100% * * 0 1 0 0 0 0 0 0 0 1 2/512 100% * * 1 0 1 1 1 1 1 1 1 1 509/512 100% * * 0 1 1 1 1 1 1 1 1 1 510/512 100% 1 0 0 0 * * 1 1 1 1 1 1 1 1 1 1 2ch pwm duty set 511/512 100% normal rotation 0 0 0 0 0 0 0 0 * * * * 0v 1 0 0 0 0 0 0 0 * * * * 1/255 vref 0 1 0 0 0 0 0 0 * * * * 2/255 vref * * * * 1 0 1 1 1 1 1 1 * * * * 253/255 vref 0 1 1 1 1 1 1 1 * * * * 254/255 vref 0 1 0 0 1 1 1 1 1 1 1 1 * * * * 1ch hall bias set (8bit dac) vref 0 0 0 0 0 0 0 0 * * * * 0v 1 0 0 0 0 0 0 0 * * * * 1/255 vref 0 1 0 0 0 0 0 0 * * * * 2/255 vref * * * * 1 0 1 1 1 1 1 1 * * * * 253/255 vref 0 1 1 1 1 1 1 1 * * * * 254/255 vref 1 1 0 0 1 1 1 1 1 1 1 1 * * * * 2ch hall bias set (8bit dac) vref 0 0 0 0 0 0 0 0 * * * * 0v 1 0 0 0 0 0 0 0 * * * * 1/255 v cc 0 1 0 0 0 0 0 0 * * * * 2/255 v cc * * * * 1 0 1 1 1 1 1 1 * * * * 253/255 v cc 0 1 1 1 1 1 1 1 * * * * 254/255 v cc 0 0 1 0 1 1 1 1 1 1 1 1 * * * * 1ch hall amplifier offset adjustment (8bit dac) v cc 0 0 0 0 0 0 0 0 * * * * 0v 1 0 0 0 0 0 0 0 * * * * 1/255 v cc 0 1 0 0 0 0 0 0 * * * * 2/255 v cc * * * * 1 0 1 1 1 1 1 1 * * * * 253/255 v cc 0 1 1 1 1 1 1 1 * * * * 254/255 v cc 1 0 1 0 1 1 1 1 1 1 1 1 * * * * 2ch hall amplifier offset adjustment (8bit dac) v cc the pwmh-bridge driver's on/off operation is done with the st pin.
lv8415cb no.a1787-9/12 hall amplifier gain setting range hall amplifier relation serial map input a0 a1 a2 a3 d0 d1 d2 d3 setting mode hall amplifier magnification ()inside: re sistance 0 0 0 0 10 (36k//3.6k) 1 0 0 0 20 (72k//3.6k) 0 1 0 0 40 (144k//3.6k) 1 1 0 0 50 (180k//3.6k) 0 0 1 0 60 (216k//3.6k) 1 0 1 0 70 (252k//3.6k) 0 1 1 0 90 (324k//3.6k) 1 1 1 0 100 (360k//3.6k) 0 0 0 1 110 (396k//3.6k) 1 0 0 1 120 (432k//3.6k) 0 1 0 1 140 (504k//3.6k) 1 1 0 1 150 (540k//3.6k) 0 0 1 1 160 (570k//3.6k) 1 0 1 1 170 (612k//3.6k) 0 1 1 1 190 (684k//3.6k) 0 0 0 1 1 1 1 1 1ch hall amplifier gain setting ( ?3? resistance ?2? resistance) 200 (720k//3.6k) 0 0 0 0 10 (36k//3.6k) 1 0 0 0 20 (72k//3.6k) 0 1 0 0 40 (144k//3.6k) 1 1 0 0 50 (180k//3.6k) 0 0 1 0 60 (216k//3.6k) 1 0 1 0 70 (252k//3.6k) 0 1 1 0 90 (324k//3.6k) 1 1 1 0 100 (360k//3.6k) 0 0 0 1 110 (396k//3.6k) 1 0 0 1 120 (432k//3.6k) 0 1 0 1 140 (504k//3.6k) 1 1 0 1 150 (540k//3.6k) 0 0 1 1 160 (570k//3.6k) 1 0 1 1 170 (612k//3.6k) 0 1 1 1 190 (684k//3.6k) 1 0 0 1 1 1 1 1 2ch hall amplifier gain setting ( ?3? resistance ?2? resistance) 200 (720k//3.6k) 0 0 0 0 10 (36k//3.6k) 1 0 0 0 20 (72k//3.6k) 0 1 0 0 40 (144k//3.6k) 1 1 0 0 50 (180k//3.6k) 0 0 1 0 60 (216k//3.6k) 1 0 1 0 70 (252k//3.6k) 0 1 1 0 90 (324k//3.6k) 1 1 1 0 100 (360k//3.6k) 0 0 0 1 110 (396k//3.6k) 1 0 0 1 120 (432k//3.6k) 0 1 0 1 140 (504k//3.6k) 1 1 0 1 150 (540k//3.6k) 0 0 1 1 160 (570k//3.6k) 1 0 1 1 170 (612k//3.6k) 0 1 1 1 190 (684k//3.6k) 0 1 0 1 1 1 1 1 1ch hall amplifier offset resistance / input resistance ( ?1? resistance ?2? resistance) 200 (720k//3.6k) 0 0 0 0 10 (36k//3.6k) 1 0 0 0 20 (72k//3.6k) 0 1 0 0 40 (144k//3.6k) 1 1 0 0 50 (180k//3.6k) 0 0 1 0 60 (216k//3.6k) 1 0 1 0 70 (252k//3.6k) 0 1 1 0 90 (324k//3.6k) 1 1 1 0 100 (360k//3.6k) 0 0 0 1 110 (396k//3.6k) 1 0 0 1 120 (432k//3.6k) 0 1 0 1 140 (504k//3.6k) 1 1 0 1 150 (540k//3.6k) 0 0 1 1 160 (570k//3.6k) 1 0 1 1 170 (612k//3.6k) 0 1 1 1 190 (684k//3.6k) 1 1 0 1 1 1 1 1 2ch hall amplifier offset resistance / input resistance ( ?1? resistance ?2? resistance) 200 (720k//3.6k)
lv8415cb no.a1787-10/12 general-purpose amplifier on/off setting input a0 a1 a2 a3 d0 d1 setting mode set content remarks 0 * stand-by 1 * general-purpose amplifier 1 operate * 0 stand-by 0 0 1 1 * 1 general-purpose amplifier 2 operate pwm circuit accuracy setting input a0 a1 a2 a3 d0 d1 setting mode set content remarks 0 0 10bit resolution initial value 0 1 11bit resolution 1 0 12bit resolution 1 0 1 1 * * pwm accuracy setting - pwm pulse width of moving 1ch (x axis side) input [3:0] a0 a1 a2 a3 d0 d1 d2 d3 setting mode moving pulse number 0 0 0 0 0 (initialization) 1 0 0 0 1 0 1 0 0 2 1 1 0 0 3 0 0 1 0 4 1 0 1 0 5 0 1 1 0 6 1 1 1 0 7 0 0 0 1 8 1 0 0 1 9 0 1 0 1 10 1 1 0 1 11 0 0 1 1 12 1 0 1 1 13 0 1 1 1 14 0 1 1 1 1 1 1 1 1ch (x axis) side width of moving 15 note : 1 pulse = 1clk 2ch (y axis side) input [7:4] a0 a1 a2 a3 d4 d5 d6 d7 setting mode moving pulse number 0 0 0 0 0 (initialization) 1 0 0 0 1 0 1 0 0 2 1 1 0 0 3 0 0 1 0 4 1 0 1 0 5 0 1 1 0 6 1 1 1 0 7 0 0 0 1 8 1 0 0 1 9 0 1 0 1 10 1 1 0 1 11 0 0 1 1 12 1 0 1 1 13 0 1 1 1 14 0 1 1 1 1 1 1 1 2ch (y axis) side width of moving 15 note : 1 pulse = 1clk the on/off operation of the hall amplifier an d the hall bias is done with the st pin. note : an initial value of a0 to a3 = 1111 is a static test mode. use it specifying data d0 for one. test mode setting input a0 a1 a2 a3 d0 setting mode content remarks 0 external clk it uses it by the shipment inspection. 1 1 1 1 1 nc pin _ test mode internal clk intern al clk operation note : external clk mode is for the shipment inspection. use it with internal clk. use it after it internal clk switches because default is external clk mode.
lv8415cb no.a1787-11/12 hall bias, offset adjustme nt circuit configuration hall amplifier, hall bias equivalent circuit about the gain adjustment the resistance ratio of ?2? and ?3? is adjusted in figure an d the gain is set. refer to the setting to the cereal map. the magnification can be set from ten by 200. about the offset adjustment the resistance ratio of ?1? and ?2? is ad justed in figure and the offset is set. refer to the setting to the cereal map. the magnification can be set from ten by 200. + - 8bit dac 8bit dac + - h 1 2 2 3 bias adjustment offset adjustment
lv8415cb ps no.a1787-12/12 sanyo semiconductor co.,ltd. assumes no responsib ility for equipment failures that result from using products at values that exceed, even momentarily, rate d values (such as maximum ra tings, operating condition ranges, or other parameters) listed in products specif ications of any and all sanyo semiconductor co.,ltd. products described or contained herein. sanyo semiconductor co.,ltd. strives to supply high-qual ity high-reliability products, however, any and all semiconductor products fail or malfunction with some probabi lity. it is possible that these probabilistic failures or malfunction could give rise to acci dents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause dam age to other property. when designing equipment, adopt safety measures so that these kinds of accidents or e vents cannot occur. such measures include but are not limited to protective circuits and error prevention c ircuits for safe design, redundant design, and structural design. upon using the technical information or products descri bed herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable f or any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. information (including circuit diagr ams and circuit parameters) herein is for example only; it is not guaranteed for volume production. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equi pment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. in the event that any or all sanyo semiconductor c o.,ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities conc erned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any in formation storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd. note in design ? stand-by function ic becomes a stand-by state at st = ?l?, and ic enters the state of operation at st =?h?. moreover, the register in ic is reset as for st = ?l? at times. ? hall bias the constant current output is built into for the hall element drive. the constant current value is set from detection resistance (rhg) connected from the hbin pin im pression voltage and the hgnd pin between gnd. constant current value (i o ) = hbin voltage detection resistance constant current value (i o ) becomes about 1ma when assuming hbin pin impressed voltage =1.0v and detection resistance = 1 k from the above-mentioned calculation type. moreover, the hgnd pin must connect with the hb pin, and connect the detection resistance of a large valu e as much as possible when you do not use the hall bias circuit. ? operation amplifier impress the bias to the v in + pin, and compose the buffer by the connection to the vout pin in the v in - pin in the operational amplifier not used. this catalog provides information as of december, 2010. specifications and inform ation herein are subject to change without notice. v cc + - h hbin hgnd hb i o v cc + - v in + v out v in -

▲Up To Search▲

Price & Availability of ENA1787A

	To Download ENA1787A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .